The invention relates to an insulated gate field effect transistor comprising a semiconductor body having a layer-shaped first region of a first conductivity type adjoining a surface, an underlying layer-shaped second region of the second opposite conductivity type, which forms a p-n junction with the first region, and at least an island-shaped zone of the second conductivity type which adjoins the surface and which is surrounded by the first region, at least a groove of V-shaped cross-section being provided in the surface, which extends through the island-shaped zone and the first region into the second region and the wall of which is coated with an electrically insulating layer, on which a conductive layer is provided which forms a gate electrode of the field effect transistor, the island-shaped zone and the second region being provided with source and drain electrodes.
The invention also relates to a method of manufacturing such a field effect transistor. A field effect transistor of the kind described is known from "Electronics", June 22.sup.nd 1978, p. 105-112.
In this transistor type, designated as a V-MOS transistor, the walls and bottom of the groove or grooves are entirely coated with an insulating layer, which is coated with a gate electrode layer, which generally also is situated above a part of the surface of the semiconductor body.
It is known that the insulating layer must then be sufficiently thin to obtain in the "ON" state a high current sensitivity and a low resistance, but also sufficiently thick to guarantee a high breakdown voltage. The disturbance of the field lines at the bottom of the groove or grooves in fact becomes larger as the thickness of the insulating layer is made smaller.
In the known methods of manufacturing V MOS transistors, it is difficult to satisfy these two criteria simultaneously.